PXD20RM Datasheet, PDF (780/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 20-8. MCR field descriptions (continued)
Field
Description
WRN_EN
LPM_ACK
D_RSVD
SRX_DIS
BCC
LPRIO_EN
Warning Interrupt Enable
When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error
and Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be
zero, independent of the values of the error counters, and no warning interrupt will ever be
generated.
1 = TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96
to  96.
0 = TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
Low Power Mode Acknowledge
This read-only bit indicates that FlexCAN is in Disable Mode. This mode cannot be entered until all
current transmission or reception processes have finished, so the CPU can poll the LPM_ACK bit
to know when FlexCAN has actually entered low power mode. See Section 20.5.9.2, Module
Disable mode, for more information.
1 = FlexCAN is either in Disable Mode
0 = FlexCAN not in any of the low power modes
Reserved bit.
This bit is writable but should be kept as value 0.
Self Reception Disable
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is
asserted, frames transmitted by the module will not be stored in any MB, regardless if the MB is
programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal
will be generated due to the frame reception.
1 = Self reception disabled
0 = Self reception enabled
Backwards Compatibility Configuration
This bit is provided to support Backwards Compatibility with previous FlexCAN versions. When this
bit is negated, the following configuration is applied:
• For MCUs supporting individual Rx ID masking, this feature is disabled. Instead of individual ID
masking per MB, FlexCAN uses its previous masking scheme with RXGMASK, RX14MASK and
RX15MASK.
• The reception queue feature is disabled. Upon receiving a message, if the first MB with a
matching ID that is found is still occupied by a previous unread message, FlexCAN will not look
for another matching MB. It will override this MB with the new message and set the CODE field
to ‘0110’ (overrun).
Upon reset this bit is negated, allowing legacy software to work without modification.
1 = Individual Rx masking and queue feature are enabled.
0 = Individual Rx masking and queue feature are disabled.
Local Priority Enable
This bit is provided for backwards compatibility reasons. It controls whether the local priority feature
is enabled or not. It is used to extend the ID used during the arbitration process. With this extended
ID concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted
ID still has 11-bit for standard frames and 29-bit for extended frames.
1 = Local Priority enabled
0 = Local Priority disabled
20-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor