PXD20RM Datasheet, PDF (1057/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
5. When the MPU detects an access error, the current AHB bus cycle is terminated with an error
response and information on the faulting reference captured in the MPU_EARn and MPU_EDRn
registers. The error-terminated AHB bus cycle typically initiates some type of error response in the
originating bus master. For example, a processor core may respond with a bus error exception,
while a data movement bus master may respond with an error interrupt. In any event, the processor
can retrieve the captured error address and detail information simply be reading the
MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is
signaled by MPU_CESR[SPERR].
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
28-19