PXD20RM Datasheet, PDF (674/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

DMA
addr
wdata[31:0]
DMA engine
hrdata[{63,31}:0]
data_path
SRAM
Transfer
Control
Descriptor (TCD)
pmodel_charb
addr_path
c
o
n
t
r
o
l
0
j
j+1
n-1
rdata[31:0]
IPS
Bus
AMBA
Bus
hwdata[{63,31}:0]
haddr[31:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 16-29. DMA operation, part 3
16.3.3 DMA performance
This section addresses the performance of the DMA module, focusing on two separate metrics. In the
traditional data movement context, performance is best expressed as the peak data transfer rates achieved
using the DMA. In most implementations, this transfer rate is limited by the speed of the source and
destination address spaces. In a second context where device-paced movement of single data values
to/from peripherals is dominant, a measure of the requests which can be serviced in a fixed time is a more
interesting metric. In this environment, the speed of the source and destination address spaces remains
important, but the microarchitecture of the DMA also factors significantly into the resulting metric.
The peak transfer rates for several different source and destination transfers are shown in Table 16-28. The
following assumptions apply to Table 16-28 and Table 16-29:
• Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data
phase
16-36
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor