PXD20RM Datasheet, PDF (1056/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

If instead the access is allowed, then the MPU simply passes all "original" AHB signals to the slave device.
In this case, from functionality point of view, the MPU is fully transparent.
28.4 Initialization information
The reset state of MPU_CESR[VLD] disables the entire module. Recall while the MPU is disabled, all
accesses from all bus masters are allowed. This state also minimizes the power dissipation of the MPU.
The power dissipation of each access evaluation macro is minimized when the associated region descriptor
is marked as invalid or when MPU_CESR[VLD] = 0.
Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup,
including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. Recall if a
memory reference does not hit in any region descriptor, the attempted access is terminated with an error.
28.5 Opcode pre-fetch cycles and the execute permission
The CPU pre-fetches program-code past the current instruction to optimize performance. The code that is
pre-fetched may never be executed or even be reachable (in the case of a branch), however the MPU
module has no way of knowing this at the time when the pre-fetch cycles occur. Therefore such pre-fetches
will result in an access violation if the opcode pre-fetch accesses a memory range in which the "x" execute
access mode is not permitted. This must be taken into account when defining memory ranges without
execute permission adjacent to memory used for program code. The best way to do this would be to leave
some fill-bytes between the memory ranges in this case — that is, do not set the upper memory boundary
to the address of the last opcode but to a following address which is several words away.
28.6 Application information
In an operational system, interfacing with the MPU can generally be classified into the following activities:
1. Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGDn, it would typically be
performed using four 32-bit word writes. As discussed in Section 28.2.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed simply by clearing
MPU_RGDn.Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAACn) would typically be performed.
Recall writes to the region descriptor using this alternate access control location do not affect the
valid bit, so there are, by definition, no coherency issues involved with the update. The access
rights associated with the memory region switch instantaneously to the new value as the IPS write
completes.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor