PXD20RM Datasheet, PDF (636/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 15-1. Interrupt registers (continued)
Register
Description
ESR
Exception syndrome register—Provides a syndrome to differentiate among the different kinds of
exceptions that generate the same interrupt type. Upon generation of a specific exception type, the
associated bits are set and all other bits are cleared.
SPE Interrupt Registers
SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control
and status as well as various condition bits associated with the operations performed by the SPE. See
Table 15-2 for a list of the associated IVORs.
Other Interrupt Registers
DEAR
Data exception address register—Contains the address that was referenced by a load, store, or cache
management instruction that caused an alignment, data TLB miss, or data storage interrupt.
IVPR
IVORs
Together, IVPR[32–47] || IVORn [48–59] || 0b0000 define the address of an interrupt-processing
routine. See Table 15-2 for more information.
MSR
Machine state register—Defines the state of the processor. When an interrupt occurs, it is updated to
preclude unrecoverable interrupts from occurring during the initial portion of the interrupt handler
Each interrupt has an associated interrupt vector address, obtained by concatenating IVPR[32–47] with the
address index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0000). The resulting
address is that of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are
indeterminate on reset and must be initialized by the system software using mtspr.
Table 15-2 lists IVOR registers implemented on the e200z4d and the associated interrupts.
Table 15-2. Exceptions and conditions
IVORn
Interrupt Type
IVORn
Interrupt Type
None¹
0²
System reset (not an interrupt)
Critical input
9
AP unavailable (not used by this core)
10 Decrementer
1
Machine check
11 Fixed-interval timer
Machine check (non-maskable interrupt)
12 Watchdog timer
2
Data storage
13 Data TLB error
3
Instruction storage
4²
External input
14 Instruction TLB error
15 Debug
5
Alignment
16–31 Reserved
6
Program
32 SPE unavailable
7
Floating-point unavailable
33 SPE data exception
8
System call
34 SPE round exception
1 _{Vector to [p_rstbase[0:29]] || 0xFFC.}
2 _{The CPU supports external vector override options on these IVORs when they are provided on the device. For}
example an INTC module may provide a separate vector for each of its sources when in hardware mode.
15-10
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor