PXD20RM Datasheet, PDF (1192/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset channel_base + 0x08
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIE TEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
TIE
TEN
Figure 32-5. Timer Control Register (TCTRL)
Table 32-6. TCTRL Field Descriptions
Description
Timer Interrupt Enable Bit.
0 Interrupt requests from Timer x are disabled
1 Interrupt will be requested whenever TIF is set
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt
event. To avoid this, the associated TIF flag must be cleared first.
Timer Enable Bit.
0 Timer will be disabled
1 Timer will be active
32.3.2.5 Timer Flag Register (TFLG)
These registers hold the PIT interrupt flags.
32-6
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor