PXD20RM Datasheet, PDF (1385/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Figure 39-60. Generation of the PWM Composite output signal
39.8 Interrupts and DMA
All of the SGM interrupt sources are ANDed together into a single interrupt vector. There are interrupt
sources related to the operation of each channel, the FIFO and DMA status and the I2S interface.
The channel interrupts and DMA are as configured and recorded in the SGM interrupt registers
(Section 39.6.2.26, SGM Interrupt Control Register (SGMIC) and Section 39.6.2.28, SGM Interrupt
Status Register (SGMIS)).
Enable the DMA for Wave mode channels using the SGMICDF[FLDECHn] bits. The status flags
SGMISDF[FLFCHn] indicate that a DMA request has been made. Note that the DMA will clear this bit
when it acknowledges the request.
There is a general timeout flag to indicate expiration of timeout counter. The counter is enabled using the
SGMCTL[TOE] bit and the interrupt control flag SGMIC[TOIE].
Interrupt sources when channels are in Wave mode:
• Playback duration over (end of each playback cycle)
• Repeat duration over
Interrupt sources when channels are in DDS mode:
• End of release phase
• End of attack phase
• End of inter-note no-output phase
• End of pulse count
The FIFO and DMA interrupts are configured and recorded in the DMA and FIFO interrupt registers
(Section 39.6.2.25, SGM Interrupt Control Register for FIFO and DMA (SGMICFD) and
Section 39.6.2.27, SGM Interrupt Status Register for FIFO and DMA (SGMISFD))
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-61