PXD20RM Datasheet, PDF (1224/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: QSPI_BASE + 0x100
Write: QSPI_SFMSR[IP_ACC] = 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
SFADR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SFADR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-5. Serial Flash Address Register (QSPI_SFAR)
Table 35-10. QSPI_SFAR Field Descriptions
Field
SFADR
Description
Serial Flash Address, register content is used as byte address for all following IP Commands.
Refer to Table 35-11 below for the address assignment related to the different access modes.
Table 35-11. SFADR Address Assignment
SFADR
Serial Flash Byte Address -
related to the first buffer entry¹
Serial Flash Device
0x7000_0000
...
0x77FF_FFFC
0x00_0000 - 0x00_0003
...
0x7FFF_FFFC - 0x7FFF_FFFF
Flash A
Refer to Section 35.5.3.4.1, Byte
Ordering in Individual Flash Mode
0x7800_0000
...
0x7FFF_FFFC
0x0000_0000 - 0x0000_0003
...
0x7FFF_FFFC - 0x7FFF_FFFF
Flash B
Refer to Section 35.5.3.4.1, Byte
Ordering in Individual Flash Mode
0x8000_0000
...
0x8FFF_FFFF
0x0000_0000 - 0x00_0001
...
0x8FFF_FFFE - 0x8FFF_FFFF
Flash B
Refer to Section 35.5.3.4.2, Byte
Ordering in Parallel Flash Mode
1 _{The address specified in the SFADR field determines the byte appearing at QSPI_RBDR0[0:7]. Subsequent bytes}
appear according to the byte ordering given above.
35.4.4.5 Instruction Code Register (QSPI_ICR)
The Instruction Code Register consists of the generic instruction code (IC) and an additional parameter
section (ICO). This contains additional options to parameterize the command as shown in Table 35-41.
If the IC field is written successfully a new command to the external serial flash device is started with that
instruction code if this code is supported by the module (see Section 35.8, Serial Flash Devices).
35-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor