PXD20RM Datasheet, PDF (260/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 9-1. XBAR Master ID Numbers (continued)
Master
VIU2
DCU3
Nexus ID
Master ID Number
5
6
8
XBAR Port ID
5
6
1
9.1.3 Unsupported features
• The max_halt_request input
• The use of the Alternate Master Priority Registers
• The use of the Alternate General Purpose Control Registers
• Registers for slave 5
• Registers for master 7
9.2 Introduction
9.2.1 Overview
This section provides an overview of the generic multi-layer AHB crossbar switch (XBAR). The purpose
of the XBAR is to concurrently support up to eight simultaneous connections between master ports and
slave ports. The XBAR supports a 64-bit address bus width and almost any data bus width at all master
and slave ports.
9.2.2 Features
The XBAR has the ability to gain control of all the slave ports and prevent any masters from making
accesses to the slave ports. This feature is useful when the user wishes to turn off the clocks to the system
and needs to ensure that no bus activity will be interrupted.
The XBAR can put each slave port into a low power park mode so that slave port will not dissipate any
power transitioning address, control or data signals when not being actively accessed by a master port.
Each slave port can also support multiple master priority schemes. Each slave port has a hardware input
which selects the master priority scheme so the user can dynamically change master priority levels on a
slave port by slave port basis.
The XBAR will allow for concurrent transactions to occur from any master port to any slave port. It is
possible for all master ports and slave ports to be in use at the same time as a result of independent master
requests. If a slave port is simultaneously requested by more than one master port, arbitration logic will
select the higher priority master and grant it ownership of the slave port. All other masters requesting that
slave port will stalled until the higher priority master completes its transactions.
PXD20 Microcontroller Reference Manual, Rev. 1
9-2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice