PXD20RM Datasheet, PDF (1295/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
The F_POR flag is automatically cleared on a 1.2V low-voltage detected
(power domain #0 or #1) or a 2.7V low-voltage detected (VREG). This
means that if the power-up sequence is not monotonic (i.e the voltage rises
and then drops enough to trigger a low-voltage detection), the F_POR flag
may not be set but instead the <register>F_LVD12_PD0,
<register>F_LVD12_PD1, or <register>F_LVD27_VREG flag is set on
exiting the reset sequence. Therefore, if the F_POR,
<register>F_LVD12_PD0, <register>F_LVD12_PD1, or
<register>F_LVD27_VREG flags are set on reset exit, software should
interpret the reset cause as power-on.
NOTE
In contrast to all other reset sources, the 1.2V low-voltage detected (power
domain #0) event is captured on its deassertion. Therefore, the status bit
F_LVD12_PD0 is also asserted on the reset’s deassertion. In case an
alternate event is selected, the SAFE mode or interrupt request are similarly
asserted on the reset’s deassertion.
37.3.1.3 Functional Event Reset Disable Register (RGM_FERD)
Address 0xC3FE_4004
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
W
POR 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-4. Functional Event Reset Disable Register (RGM_FERD)
This register provides dedicated bits to disable functional reset sources.When a functional reset source is
disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request
(see Section 37.3.1.5, Functional Event Alternate Request Register (RGM_FEAR)). It can be accessed in
read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte
can be written only once after power-on reset.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
37-19