PXD20RM Datasheet, PDF (273/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

if a particular slave port would temporarily benefit from modifying the master priority levels or functions
affected by the bits in the SGPCR.
9.4.2.2 Priority Elevation
The XBAR has a hardware input per master port (mX_high_priority) which is used to temporarily elevate
the master’s priority level on all slave ports. When the master’s mX_high_priority input is asserted the
master port will automatically have higher priority than all other master ports that do not have their
mX_high_priority input asserted regardless of the priority levels programmed in the MPR and AMPR. If
multiple master ports have their mX_high_priority input asserted they will have higher priority than all
master ports which do not have their mX_high_priority inputs asserted. The MPR or AMPR priority level
(dependent on the state of sX_ampr_sel) will determine which master port that has its mX_high_priority
input asserted has the highest priority on a slave port by slave port basis.
This functionality is useful because it allows the user to automatically elevate a master port’s priority level
throughout the XBAR in order to quickly perform temporary tasks such as servicing interrupts.
Please note that the HPEx bits must be set in the SGPCR or ASGPCR in the slave port in order for the
mX_high_priority inputs to be received by the slave port.
9.4.3 Master Port Functionality
9.4.3.1 General
Each master port consists of two decoders, a capture unit, a register slice, a mux and a small state machine.
The first decoder is used to decode the mX_hsel_slv and control signals coming directly from the master,
telling the state machine where the master’s next access will be and if it is in fact a legal access. The second
decoder receives its input from the capture unit, so it may be looking directly at the signals coming from
the master or it may be looking at captured signals coming from the master, depending entirely on the state
of the targeted slave port. The second decoder is then used to generate the access requests that go to the
slave ports.
The capture unit is used to capture the address and control information coming from the master in the event
that the targeted slave port cannot immediately service the master. The capture unit is controlled by outputs
from the state machine which tell it to either pass through the original master signals or the captured
signals.
The register slice contains the registers associated with the specific master port. The registers have a
quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine.
The mux is used simply to select which slave’s read data is sent back to the master. The mux is controlled
by the state machine.
The state machine controls all aspects of the master port. It knows which slave port the master wants to
make a request to and controls when that request is made. It also has knowledge of each slave port,
knowing whether or not the slave port is ready to accept an access from the master port. This will
determine whether or not the master may immediately have its request taken by the slave port or whether
the master port will have to capture the master’s request and queue it at the slave port boundary.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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