PXD20RM Datasheet, PDF (739/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Figure 18-30 describes the operation of the OPWMB mode regarding A1 and B1 matches and the
transition of the channel output pin. In this example EDPOL is set to zero.
clock
prescaler
write to A2
cycle n
cycle n+1
Selected
counter bus
1
A1 value
A2 value
B1 value
0x000004
0x000006
A1 match
A1 match posedge detection
A1 match negedge detection
4
0x000000
6
6
1
0x000000
match A1 negedge detection
match A1 posedge detection
8
TIME
B1 match
B1 match negedge detection
output pin
EDPOL = 0
FLAG set event
FLAG pin/register
match B1 negedge detection
Figure 18-30. OPWMB Mode Matches and Flags
Note that the output pin transitions are based on the negedges of the A1 and B1 match signals.
Figure 18-30 shows in cycle n+1 the value of A1 register being set to zero. In this case the match posedge
is used instead of the negedge to transition the output flip-flop.
Figure 18-31 describes the channel operation for 0% duty cycle. Note that the A1 match posedge signal
occurs at the same time as the B1=0x8 negedge signal. In this case A1 match has precedence over B1
match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-37