PXD20RM Datasheet, PDF (794/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Base + 0x002C
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R _{BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF}
W ^63I
62I
61I
60I
59I
58I
57I
56I
55I
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53I
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50I
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48I
RESET: ₀
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R _{BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF BUF}
W ^47I
46I
45I
44I
43I
42I
41I
40I
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32I
RESET: ₀
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Figure 20-13. Interrupt Flag Register High (IFRH)
Table 20-16. IFRH field descriptions
Field
BUF32I –
BUF63I
Description
Buffer MB_i Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB32 to MB63) interrupt.
1 = The corresponding buffer has successfully completed transmission or reception
0 = No such occurrence
20.4.4.12 Interrupt Flag Register Low (IFRL)
This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It contains one
interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFRL bit. If
the corresponding IMRL bit is set, an interrupt will be generated. The Interrupt flag must be cleared by
writing it to ‘1’. Writing ‘0’ has no effect.
When the MCR[FEN] is set (FIFO enabled), the function of the 8 least significant interrupt flags (BUF7I
- BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating
conditions of the FIFO, while BUF4I to BUF0I are not used.
20-28
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor