PXD20RM Datasheet, PDF (945/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

26.6.1.3 Unique Vector for Each Interrupt Request Source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.
Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt
requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The
peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired
vectors within the INTC.
26.6.2 Priority Management
The asserted interrupt requests are compared to each other based on their PRIx values set in
INTC_PSR0_3–INTC_PSR236_238. The result is compared to PRI in the associated INTC_CPR. The
results of those comparisons manage the priority of the ISR executed by the associated processor. The
associated LIFO also assists in managing that priority.
26.6.2.1 Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 26-1 compare the
priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or
software configurable interrupt request is higher than the current priority for a given processor, then the
interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or
software settable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR),
and if in hardware vector mode, for the interrupt vector provided to the processor.
26.6.2.1.1 Priority Arbitrator Subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software configurable. The output of the priority
arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt
requests which have this highest priority are output as asserted interrupt requests to the associated request
selector subblock.
26.6.2.1.2 Request Selector Subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed
as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated
priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the
associated vector encoder subblock. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software configurable interrupt requests.
26.6.2.1.3 Vector Encoder Subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the
request selector subblock for the associated processor.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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