PXD20RM Datasheet, PDF (1530/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

46.4 Functional description
The major functions of the TCON are to generate timing signals needed to drive the external row drivers
and column drivers, and map the RGB data bits to the outputs according to the RSDS^TM standard. It
accepts RGB data, and Horizontal/Vertical synchronization signals from the Display Controller Unit
module, maintains two internal counters (x_count, and y_count), and uses these to generate the timing
signals. In order to support as many type of panels aspossible, the timing generation unit has been designed
to be flexible and can be configured freely to generate complicated timing signals. See Section 46.4.2,
Timing signal generator, for details about the timing signal generation unit.
The TCON has three operation modes including RSDS mode, TTL mode, and bypass mode. In bypass
mode the input signals are passed through the TCON unchanged, and in the other two modes the TCON
performs signal (the RGB data and pixel clock) bit mapping. For details of the operation modes see
Section 46.4.1, Modes of operation, and for the signal bit mapping see Section 46.4.4, Bit Mapping
Control (BMC).
The TCON also has a data inversion control feature which can be used to minimize transitions on the
output data bus. For details see Section 46.4.3, Data inversion control.
46.4.1 Modes of operation
46.4.1.1 RSDS mode
The RSDS mode is the typical operation mode of the TCON. In RSDS mode, the TCON maps the RGB
data bits and the pixel clock according to the RSDS^TM “Intra-panel“ interface specification, revision 1.0
(National Semiconductor). For details see Section 46.4.4.2, Bit mapping in RSDS mode.
In RSDS mode, the TCON drives the RSDS interface, where the RGB data and the pixel clock (25 signals
for 8-bit color depth, and 19 signals for 6-bit color depth) are transfered via 13 or 10 RSDS differential
pairs, each differential pair carries two signals. So data is driven on both rising and falling edge of the pixel
clock. The TCON timing signals are transfered via single ended TTL interface.
In RSDS mode, the TCON places the RSDS I/O in RSDS output mode.
To ease board design, the pixel clock can be assigned to any one of the differential pairs. See
Section 46.4.4.4, Clock mapping in RSDS mode.
To enable the RSDS mode, set TCON_CTRL1[RSDS_MODE]=’1’,
TCON_CTRL1[TCON_BYPASS]=’0’, and TCON_CTRL1[TCON_EN]=’1’. For the TCON_CTRL1
register see Section 46.3.3.1, Control Register 1 (TCON_CTRL1).
46.4.1.2 TTL mode
In TTL mode the TCON drives the RGB data, pixel clock, and the TCON timing signals all via TTL
interface. In this mode simpler signal bit mapping is performed, see Section 46.4.4.1, Bit mapping in TTL
mode.
It is also possible to assign the pixel clock to any one of the 25 output pins in TTL mode, see
Section 46.4.4.5, Clock mapping in TTL mode.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor