PXD20RM Datasheet, PDF (759/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Register address: ECSM Base + 0x56
0
1
2
3
4
5
6
7
R
0
0
0
0
FEMR[0:3]
W
RESET:
0
0
0
0
-
-
-
-
= Unimplemented
Figure 19-6. Flash ECC Master Number (FEMR) Register
Table 19-7. Flash ECC Master Number (FEMR) Field Descriptions
Name
4-7
FEMR[0:3]
Description
Flash ECC Master Number Register
This 4-bit register contains the AXBS bus master number of the faulting access of the last,
properly-enabled flash ECC event.
19.4.2.8 Flash ECC Attributes (FEAT) register
The FEAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,
FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 19-7 and Table 19-8 for the Flash ECC Attributes Register definition.
Register address: ECSM Base + 0x57
0
1
2
3
4
5
6
7
R
Write
Size[0:2]
Protection[0:3]
W
RESET:
x
x
x
x
x
x
x
x
Name
0
Write
= Unimplemented
Figure 19-7. Flash ECC Attributes (FEAT) Register
Table 19-8. Flash ECC Attributes (FEAT) Field Descriptions
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
Description
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-11