PXD20RM Datasheet, PDF (600/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

incorrect time, or produces not enough or too many read strobes, the DRAMC may detect some
error conditions because they result in an overflow or underflow of the FIFO that keeps track of
the number of outstanding DQS pulses. These bits do not detect timing configuration errors.
Underflows and overflows signaled by the read FIFO point to following possible error sources:
— Incorrect configuration of the DRAM. Burst length set incorrectly
— Incorrect configuration of the DRAMC.
– Incorrect RDLY
– Incorrect H_DQSDLY
– Incorrect Q_DQSDLY
– Incorrect DRAM timing parameters or mis-match between various settings.
— Problems with the electrical connections between the DRAMC and the DRAM
• It contains a bypass path to send commands to the DRAM. This is because the DRAMC contains
no logic to take care of DRAM initialization, programming the mode registers, or putting the
DRAM into or out of the sleep and standby modes like self-refresh. Essentially, these functions are
made available over the peripheral bus. To program the mode registers, the DRAMC needs to be
put in a bypass mode, where incoming requests are not serviced. In this bypass mode, commands
are sent from the peripheral interface directly to the DRAM to program the mode registers or to put
the DRAM into or out of sleep mode.
• During bypass mode, all reads and writes are blocked. Refresh keeps running, but can be separately
disabled.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor