PXD20RM Datasheet, PDF (1127/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 30-10. WT Field Descriptions
Field
Description
0–2
PTS[2:0]
Program Trace Start Control.
000 Trigger disabled.
001 Use watchpoint #0 (IAC1 from Nexus1).
010 Use watchpoint #1 (IAC2 from Nexus1).
011 Use watchpoint #2 (IAC3 from Nexus1).
100 Use watchpoint #3 (IAC4 from Nexus1).
101 Use watchpoint #4 (DAC1 from Nexus1).
110 Use watchpoint #5 (DAC2 from Nexus1).
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1).
3–5
PTE[2:0]
Program Trace End Control.
000 Trigger disabled.
001 Use watchpoint #0 (IAC1 from Nexus1).
010 Use watchpoint #1 (IAC2 from Nexus1).
011 Use watchpoint #2 (IAC3 from Nexus1).
100 Use watchpoint #3 (IAC4 from Nexus1).
101 Use watchpoint #4 (DAC1 from Nexus1).
110 Use watchpoint #5 (DAC2 from Nexus1).
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1).
12–31 Reserved.
30.7 Functional Description
The NDI block is implemented by integrating the following blocks on this device:
• Nexus e200z4d development interface (OnCE and Nexus3 subblocks)
• Nexus port controller (NPC) Block
• NPC_HNDSHK module
30.7.1 NPC_HNDSHK module
This module enables debug entry/exit across low power modes(Stop, Halt, standby) .
The NPC_HNDSHK supports:
• Setting and clearing of the NPC PCR sync bit on low-power mode entry and exit
• Putting the CPU into debug mode on low-power mode exit
• Generating a falling edge on the JTAG TDO pad on low-power mode exit
On HALT, STOP, or STANDBY mode entry, the MC_ME asserts the lp_mode_entry_req input after the
clock disable process has completed and before the processor enters its halted or stopped state. The mode
transition will then not proceed until the lp_mode_entry_ack output has been asserted. The notification to
the debugger of a low-power mode entry consists of setting the low-power mode handshake bit in the port
control register (read by the debugger) via the lp_sync_in output. The debugger acknowledges that the
transition into a low-power mode may proceed by clearing the low-power mode handshake bit in the port
control register (written by the debugger), which results in the deassertion of the lp_sync_out input.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-15