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PXD20RM Datasheet, PDF (1563/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller
47.2.3.15 LUT_DATA
Offset 0x38
Access: User read/write
0
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R
DATA[31:16]
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Reset 0
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DATA[15:0]
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Reset 0
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= Unimplemented or Reserved
Figure 47-16. LUT_DATA Register
Table 47-17. LUT_DATA Fields
Field
DATA
Description
B/C adjust look-up-table data entry. Data in this register is actually written/read to/from the address
pointed by the current LUT_ADDR value in the table.
Note: DATA reflects correct data value only when clock of B/C adjust block is valid.
47.3 Functional Description
The VIU2 accepts ITU-R BT.656 compatible video stream on its parallel interface, decodes it and
optionally performs processes like down-scaling, brightness and contrast adjust, YUV to RGB conversion,
and de-interlace (weaving), and then stores the result video stream to the system memory which can then
be displayed by a display controller, or post processed.
Functions of the VIU2 are designed in a way that they can be flexibly enabled or disable by software. But
there are a few limitations as listed below:
• The down-scaler works on YUV 4:2:2 format, so to enable the down-scaler ITU decoder shall be
configured in YUV 4:2:2 mode.
• To use the down-scaler, progressive video input shall be used for display quality’s sake, and the
de-interlace shall be disabled.
47.3.1 ITU656
The ITU-R BT.656-4 recommendation describes the means of interconnecting digital television equipment
operating on the 525-line or 625-line standards and combines with the 4:2:2 encoding parameters as
defined in the ITU-R BT.601 recommendation.
The data stream structure on ITU-R BT.656-4 interface is shown in Figure 47-17. There are two timing
reference signals, one at the beginning of each video data block (start of active video, SAV) and one at the
end of each video data block (end of active video, EAV).
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
47-15