PXD20RM Datasheet, PDF (878/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

23.2.2.2 PRAM2P Status Register (PRAM2P_SR)
The PRAM2P_SR is s read only register containing the RAM array busy flag. All writes to this register
will return an error.
Offset 0x4
Access: User read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 BUSY
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-3. PRAM2P Control Register(PRAM2P_CR)
Table 23-3. PRAM2P_CR Field Descriptions
Field
Description
BUSY
When a Fill operation is in progress, the portion of the array that is “to be filled” is unavailable and accesses to those
area will be returned with an error. Areas not targeted as well as areas that have already been filled are accessible
and can interrupt the Fill operation's access to the array. The BUSY bit indicates that a Fill operation is in progress.
0 Array is available.
1 A Fill operation is in progress.
23.2.2.3 PRAM2P Fill Region Begin Address Register (PRAM2P_BEG)
Offset 0x8
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0
W
BEG_ADDR[23:4]
0000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 23-4. PRAM2P Fill Region Begin Address Register (PRAM2P_BEG)
Table 23-4. PRAM2P_BEG Field Descriptions
Field
Description
BEG_ Fill operation will begin at GSRAM base address + {BEG_ADDR[23:4],4’b0}. While the GSRAM is busy filling
ADDR indicated by the BUSY bit in the PRAM2P_SR, this register will not be writable. Any write access to this register will
[23:4] return an error.
23-4
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor