PXD20RM Datasheet, PDF (1608/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 50-4. MSR field descriptions
Field
UCLE
SPE
WE
CE
EE
PR
FP
ME
DE
IS
DS
RI
Description
User Cache Lock Enable
SPE Available
0: Execution of SPE APU vector instructions is disabled; SPE Unavailable exception taken instead, and
SPE bit is set in ESR.
1: Execution of SPE APU vector instructions is enabled.
Wait State (Power management) enable
Critical Interrupt Enable
External Interrupt Enable
Problem State
Floating-Point Available
Machine Check Enable
Debug Interrupt Enable
Instruction Address Space
Data Address Space
Recoverable Interrupt
50.4.3 Hardware single precision floating point
The SPE-APU also supports 32-bit IEEE^®-754 single-precision floating-point formats, and supports
vector and scalar single-precision floating-point operations. Most compiler vendors include libraries that
can emulate floating point functionality. However, by specifying the correct compiler options, the single
precision floating point instructions may be used.
To enable use of hardware floating point the MSR[SPE] field must be set. Refer to Section 50.4.2, Signal
processing extension for register details.
50.4.4 Variable length encoding
In addition to the base Power Architecture instruction set support, the e200z4d core also implements the
VLE (variable-length encoding) APU, providing improved code density. The VLE-APU can be viewed as
a supplement to the existing Power Architecture instruction set that can be conditionally applied to a
portion of, or an entire application for which improved code density is desired.
Using it is straightforward:
1. Select the appropriate compiler target and option to generate VLE code.
2. Configure the Memory Management Unit (MMU) to specify VLE attributes for the relevant MMU
pages. Refer to the register description in Section 50.3.6, Memory management unit (MMU).
VLE-enabled cores run both Power Architecture and VLE instruction encodings on a page by page basis,
with pages defined by the MMU. The reduction is code size is typically between 25% and 30%.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor