PXD20RM Datasheet, PDF (1490/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: Base + 0x0C80 - 0x0CA8 (12 registers)
0
1
2
3
4
5
6
7
8
9
R₀
0
0
0
0
0
0
0
0
0
W
MASK[x][0:15]
Reset ₀
0
0
0
0
0
0
0
0
0
Access: User read/write
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
MPPDO[x][0:15]
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 43-18. Masked Parallel GPIO Pad Data Out Register (MPGPDO0)
Table 43-19. MPGPDO0_3 field descriptions
Field
Description
MASK[x][0:15]
Mask Field
Each bit corresponds to one data bit in the MPPDO[x] register at the same bit location.
1: The associated bit value in the MPPDO[x] field is written
0: The associated bit value in the MPPDO[x] field is ignored
MPPDO[x][0:15] Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data
Output Registers (GPDO0_3 - GPDO184).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[x][y] = PDO[(x*16)+y]
NOTE
It is important to note the bit ordering of the ports in the parallel port
registers. The most significant bit of the parallel port register corresponds to
the least significant pin in the port.
WARNING
Toggling several IOs at the same time can significantly increase the current
in a pad group. Caution must be taken to avoid exceeding maximum current
thresholds. Please refer to data sheet.
43.5.3.16 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)
These registers are used to configure the filter counter associated with each digital glitch filter.
NOTE
For the pad transition to trigger an interrupt it must be steady for at least the
filter period.
43-24
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor