PXD20RM Datasheet, PDF (952/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 26-10. Order of ISR Execution Example (continued)
Step
Step Description
Code Executing at End of Step
PRI in
RTOS
ISR108¹
ISR208
ISR308
ISR408
Interrupt
Exception
Handler
INTC_CPR
at End of
Step
8 ISR208 completes. Interrupt
exception handler writes to
INTC_EOIR.
X
1
9 Interrupt taken. ISR308 starts to
execute.
X
3
10 ISR308 completes. Interrupt
exception handler writes to
INTC_EOIR.
X
1
11 ISR108 completes. Interrupt
exception handler writes to
INTC_EOIR.
X
0
12 RTOS continues execution.
X
0
1 _{ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable}
interrupt requests.
26.7.5 Priority Ceiling Protocol
26.7.5.1 Elevating Priority
The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs
that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource.
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in
INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can
preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is
deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can
continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and
execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when
accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot
preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can
preempt ISR1.
26.7.5.2 Ensuring coherency
A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both
running on the same CPU and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor