PXD20RM Datasheet, PDF (236/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 8-27. CR field descriptions (continued)
Field
Description
en_pll_sw
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially is
divided by 8 then progressively divides down until divide by 1.
0 => progressive clock switching disabled
1 => progressive clock switching enabled
Note: The PLL output should not be used if a non-changing clock is needed (such as for serial
communications) until the division has finished
mode
This bit is used to activate the 1:1 Mode.
unlock_once This bit is a sticky indication of PLL loss of lock condition. Unlock_once is set when the PLL loses
lock. Whenever the PLL reacquires lock, unlock_once remains set. Only a power-on reset can clear
this bit.
i_lock This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing 1.
s_lock
This bit is an indication of whether the PLL has acquired lock.
0 => PLL unlocked
1 => PLL locked
pll_fail_mask This bit is used to mask the pll_fail output.
0 => pll_fail not masked
1 => pll_fail masked
pll_fail_flag This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is
switched on. It is cleared by software, writing 1.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Table 8-28. Input divide ratios
IDF
Input divide ratio (R_INP)
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
Divide by 11
Divide by 12
Divide by 13
Divide by 14
8-40
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor