PXD20RM Datasheet, PDF (729/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

18.7.1.1.1 General purpose Input/Output mode (GPIO) Mode
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter
(CCNTR[n]) is cleared and disabled. All control bits remain accessible. In order to prepare the UC for a
new operation mode, writing to CADR[n] or CBDR[n] stores the same value in registers A1/A2 or B1/B2,
respectively. Writing to ALTCADR[n] stores a value only in register A2.
MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
CAUTION
When changing MODE[0:6], the application software must go to GPIO
mode first in order to reset the UC’s internal functions properly. Failure to
do this could lead to invalid and unexpected output compare or input capture
results or the FLAGs being set incorrectly.
In GPIO input mode (MODE[0:6]=0000000), the FLAG generation is determined according to EDPOL
and EDSEL bits and the input pin status can be determined by reading the UCIN bit.
In GPIO output mode (MODE[0:6]=0000001), the Unified Channel is used as a single output port pin and
the value of the EDPOL bit is permanently transferred to the output flip-flop.
18.7.1.1.2 Single Action Input Capture (SAIC) Mode
In SAIC mode (MODE[0:6]=0000010), when a triggering event occurs on the input pin, the value on the
selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate
that an input capture has occurred. CADR[n] returns the value of register A2. As soon as the SAIC mode
is entered coming out from GPIO mode the channel is ready to capture events. The events are captured as
soon as they occur thus reading register A always returns the value of the latest captured event. Subsequent
captures are enabled with no need of further reads from CADR[n]. The FLAG is set at any time a new
event is captured.
The input capture is triggered by a rising, falling or either edges in the input pin, as configured by the
EDPOL and EDSEL bits in CCR[n].
Figure 18-17 and Figure 18-18 shows how the Unified Channel can be used for input capture.
EDSEL = 0
EDPOL = 1
input signal¹
selected counter bus
FLAG pin/register
0x000500
Edge detect
0x001000
0x001100
Edge detect
0x001250
Edge detect
0x001525
0x0016A0
A2 (captured) value²
0xxxxxxx
0x001000
0x001250
0x0016A0
Notes: 1. After input filter
2. CADR[n] <= A2
Figure 18-17. Single Action Input Capture with rising edge triggering example
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-27