PXD20RM Datasheet, PDF (723/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 18-18. CSR[n] field descriptions
Field
OVR
OVFL
UCIN
UCOUT
FLAG
Description
Overrun bit. The OVR bit indicates that FLAG generation occurred when the FLAG bit was already
set.
1 = Overrun has occurred
0 = Overrun has not occurred
Overflow bit. The OVFL bit indicates that an overflow has occurred in the internal counter. OVFL must
be cleared by software writing a 1 to the OVFLC bit.
1 = An overflow has occurred
0 = No overflow
Unified Channel Input pin bit. The UCIN bit reflects the input pin state after being filtered and
synchronized.
Unified Channel Output pin bit. The UCOUT bit reflects the output pin state.
Flag bit. The FLAG bit is set when an input capture or a match event in the comparators occurred.
1 = FLAG set event has occurred
0 = FLAG cleared
Note: emios_flag_out reflects the FLAG bit value. When DMA bit is set, the FLAG bit can be cleared
by the DMA controller.
18.6.2.10 eMIOS200 UC Alternate A Register (ALTCADR[n])
ALTCADR[n] address: UC[n] base address + 0x14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0000000000000000
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ALTCADR
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 18-13. eMIOS200 UC Alternate A Register (ALTCADR[n])
The ALTCADR[n] provides an alternate address to access A2 channel registers in restricted modes (GPIO)
only. If CADR[n] is used along with ALTCADR[n], both A1 and A2 registers can be accessed in these
modes. Table 18-11 summarizes the ALTCADR[n] writing and reading accesses for all operation modes.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-21