PXD20RM Datasheet, PDF (495/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
BP_V
PW_V
FP_V
Table 12-21. VSYN_PARA field descriptions
Description
VSYNC back-porch pulse width (in pixel clock cycles)
VSYNC active pulse width (in pixel clock cycles).
VSYNC front-porch pulse width (in pixel clock cycles)
12.3.4.17 SYN_POL Register
Figure 12-20 represents the SYN_POL register. SYN_POL register selects polarity for corresponding
synchronize signals (HSYNC, VSYNC, CSYNC), and controls the bypass of HSYNC or VSYNC with
CSYNC signal.
Offset 0x1E4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-20. SYN_POL Register
Table 12-22. SYN_POL field descriptions
Field
INV_PDI_DE
INV_PDI_HS
INV_PDI_VS
INV_PDI_CLK
Description
Polarity change of PDI input data Enable.
1’b0: DE is active high
1’b1: DE is active low
Polarity change of PDI input HSYNC.
1’b0: HSYNC is active high
1’b1: HSYNC is active low
Polarity change of PDI input VSYNC.
1’b0: VSYNC is active high
1’b1: VSYNC is active low
Polarity change of PDI input Clock.
1’b0: DCULite samples data on the rising edge
1’b1: DCULite samples data on the falling edge
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-33