PXD20RM Datasheet, PDF (720/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
EDSEL
EDPOL
MODE
Table 18-12. CCR[n] field descriptions (continued)
Description
Edge Selection bit
For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a
pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of operation
description, this bit has no effect.
1 = Both edges triggering
0 = Single edge triggering defined by the EDPOL bit
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
1 = No FLAG is generated
0 = A FLAG is generated as defined by the EDPOL bit
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
1 = The output flip-flop is toggled
0 = The EDPOL value is transferred to the output flip-flop
Edge Polarity bit
For input modes (except QDEC mode), the EDPOL bit asserts which edge triggers either the internal
counter or an input capture or a FLAG. When not shown in the mode of operation description, this bit
has no effect.
1 = Trigger on a rising edge
0 = Trigger on a falling edge
For QDEC (MODE[6] cleared), the EDPOL bit selects the count direction according to direction signal
(UC[n] input).
1 = counts up when UC[n] is asserted
0 = counts down when UC[n] is asserted
Note: UC[n-1] EDPOL bit selects which edge clocks the internal counter of UC[n]
1 = Trigger on a rising edge
0 = Trigger on a falling edge
For QDEC (MODE[6] set), the EDPOL bit selects the count direction according to the phase
difference.
1 = internal counter increments if phase_A is ahead phase_B signal
0 = internal counter decrements if phase_A is ahead phase_B signal
Note: In order to operate properly, EDPOL bit must contain the same value in UC[n] and UC[n-1]
For output modes, the EDPOL bit is used to select the logic level on the output pin.
1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it
0 = A match on comparator A clears the output flip-flop, while a match on comparator B sets it
Mode selection bits
The MODE[0:6] bits select the mode of operation of the Unified Channel, as shown in Table 18-17.
Note: If a reserved value is written to mode the results are unpredictable.
ODISSL[0:1]
00
01
10
11
Table 18-13. UC ODISSL selection
eMIOS0 channel
emios_flag_out[8]
emios_flag_out[9]
emios_flag_out[10]
emios_flag_out[11]
eMIOS1 channel
emios_flag_out[8]
emios_flag_out[9]
emios_flag_out[10]
emios_flag_out[11]
input signal
Output Disable Input 0
Output Disable Input 1
Output Disable Input 2
Output Disable Input 3
18-18
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor