PXD20RM Datasheet, PDF (735/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Prescaler ratio = 2
system clock
prescaler
EMIOSCNT
1
A1 value
B1 value
A1 match
0x000004
0x000008
A1 match negedge detection
B1 match
8
5
4
match A1 negedge detection
TIME
match B1 negedge detection
B1 match negedge detection
output pin
EDPOL = 0
Figure 18-25. OPWFMB A1 and B1 match to Output Register Delay
Figure 18-26 describes the generated output signal if A1 is set to 0x0. Since the counter does not reach
zero in this mode, the channel internal logic infers a match as if A1=0x1 with the difference that in this
case, the posedge of the match signal is used to trigger the output pin transition instead of the negedge used
when A1=0x1. Note that A1 posedge match signal from cycle n+1 occurs at the same time as B1 negedge
match signal from cycle n. This allows to use the A1 posedge match to mask the B1 negedge match when
they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty
cycle is generated.
write to A2
cycle n
cycle n+1
system clock
prescaler
EMIOSCNT
1
A1 value
A2 value
B1 value
0x000004
0x000008
A1 match
A1 match posedge detection
A1 match negedge detection
4
0x000000
5
1
TIME
0x000000
match A1 negedge detection
match A1 posedge detection
B1 match
B1 match negedge detection
match B1 negedge detection
Prescaler ratio = 2
output pin
EDPOL = 0
no transition at this point
Figure 18-26. OPWFMB Mode with A1 = 0 (0% duty cycle)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-33