PXD20RM Datasheet, PDF (599/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The logic keeping track of what is currently possible on each of the banks is not in the DRAM command
engine. It is part of the timing manager, whose task is to signal to the DRAM command engine that
commands are currently possible.
13.4.4 Write Buffer
All incoming writes are sent first to the write buffer, part of the command engine. Writes are sent to the
DRAM in background, whenever possible. The DRAM tries to postpone the writes until there are no
further outstanding read requests. However, when the write buffer is full, or when there is a new request
for an address already inside the write buffer, the DRAMC writes the content of the write buffer to the
DRAM.
13.4.5 Timing Manager
The timing manager consists of a bank of counters. These counters keeps track of all DRAM timing
parameters and signals to the DRAM command engine when a precharge, activate, read or write command
is possible. This information is supplied to the DRAM command engine for each bank separately.
All timing parameters are programmable in software.
13.4.6 DRAM Read Block and DRAM Write Block
Sending a read or write command to the DRAM is a two-step process. First, the command is sent, which
is done by the command engine. After some clock cycles, the data must follow.
Manipulating the read data is done by the read block. For every read command sent to the DRAM, the
command engine informs the read block. Upon receiving the read command, the read block delays this to
account for DRAM pipelining. Then, it receives the correct amount of data from the DRAM DQ inputs
and forwards this data to the correct bus.
Manipulating the write data is done by the write block. It works the same way as the read block. The
command engine informs the write block of a pending write. Upon receiving the command, the write block
delays this to account for DRAM pipelining. Then, it receives the relevant data from the write buffer and
transmits this to the DRAM.
13.4.7 Bus Interface
The bus interface accepts a slave peripheral bus. The bus interface fulfills several functions:
• It contains all configuration registers
• It contains logic to send an error interrupt to the processor. The error interrupt is active when the
FIFO overflow or FIFO underflow error condition and corresponding interrupt enable in register
DRAMC_SCR is set. The register summary is given in Table 13-1.
The FIFO overflow and underflow flags are tied to a FIFO that keeps track of the number of DQS
strobes the DRAM is expected to produce. If a read command is sent to the DRAM, the DRAM is
expected to answer after producing the read data on its DQ outputs, with some edges on its DQS
output used by the controller to clock the read data. If the DRAMC produces the read strobes at an
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-19