PXD20RM Datasheet, PDF (1108/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from
the specified mode values (i.e., a non-existing mode), an invalid mode transition event is generated.
When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This
condition is detected regardless of whether the proper key mechanism is followed while writing
the ME_MCTL register.
• If some of the device modes are disabled as programmed in the ME_ME register, their respective
configurations are considered reserved, and any access to the ME_MCTL register with those
values results in an invalid mode transition request. When such a disabled mode is requested, the
S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the
proper key mechanism is followed while writing the ME_MCTL register.
• If the target mode is not a valid mode with respect to the current mode, the mode request illegal
status bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper
key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation
is ignored.
• If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of
the ME_GS register is ‘1’), the mode transition illegal status bit S_MTI of the ME_IMTS register
is set. This condition is detected only when the proper key mechanism is followed while writing
the ME_MCTL register. Otherwise, the write operation is ignored.
NOTE
As the causes of invalid mode transitions may overlap at the same time, the
priority implemented for invalid mode transition status bits of the
ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA,
S_DMA, S_MRI, and S_MTI.
As an exception, the mode transition request is not considered as invalid under the following conditions:
• A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition
status.
• As the exit of HALT and STOP modes depends on the interrupts of the system which can occur at
any instant, these requests to return to RUN0…3 modes are always valid.
• In order to avoid any unwanted lockup of the device modes, software can abort a mode transition
by requesting the parent mode if, for example, the mode transition has not completed after a
software determined ‘reasonable’ amount of time for whatever reason. The parent mode is the
device mode before a valid mode request was made.
• Self-transition requests (e.g., RUN0  RUN0) are not considered as invalid even when the mode
transition process is active (i.e., S_MTRANS is ‘1’). During the low-power mode exit process, if
the system is not able to enter the respective RUN0…3 mode properly (i.e., all status bits of the
ME_GS register match with configuration bits in the ME_<mode>_MC register), then software
can only request the SAFE or RESET mode. It is not possible to request any other mode or to go
back to the low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register
is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor