PXD20RM Datasheet, PDF (1254/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

35.6.3 Exclusive Access to Serial Flash for AHB Commands
It is possible that several masters need to access the serial flash device connected to the QuadSPI module
separately, one master by triggering IP Commands and reading the RX Buffer and the other masters by
triggering AHB Commands. To avoid command collisions resulting in excessive latencies the QuadSPI
module implements a request-handshake mechanism between the master triggering AHB Commands and
the QuadSPI module allowing this specific master to request exclusive access to the serial flash device for
AHB Commands. If this exclusive access is granted the execution of IP Commands is blocked. This
resolves command collisions and excessive times where the AHB interface may be blocked.
If this capability is used in the device there is additional status and flag information available related to
this mechanism. The QSPI_SFMSR[AHBGNT] bit reflects the module-internal state that the exclusive
access mentioned above is granted, any attempt to trigger an IP Command is rejected and results in the
assertion of the QSPI_SFMFR[IPGEF] flag. Refer to the descriptions of the related bit and flag for details.
It is within the responsibility of the application to set up the master using this mechanism appropriately, if
used incorrectly no IP Commands at all can be triggered.
Two different cases can be distinguished:
35.6.3.1 RX Buffer Read via QSPI_ARDB Registers
In this case all masters share the AHB bus for RX Buffer as well as for AHB Buffer read. In this case the
access to the AHB interface by the master triggering AHB Commands must be deferred until any pending
IP Command has been finished and the RX Buffer readout has been finished as well. This is the
conservative use case, corresponding to the reset value 0 of the QSPI_RBCT[RXBRD] bit.
In this case the QSPI_SFMSR[AHBGNT] bit is asserted not earlier than any running IP Command has
been finished (QSPI_SFMSR[IP_ACC] is 0), the RX Buffer has been read out completely
(QSPI_RBSR[RDBFL] equal to 0) and no DMA read is pending (QSPI_SFMSR[RXDMA] equal to 0.
35.6.3.2 RX Buffer Read via QSPI_RDBR Registers
This is the preferred use case. It is not possible that a pending AHB bus access triggered by an AHB
Command stalls the AHB bus and blocks the RX Buffer readout since the RX Buffer is read via the IP bus
based registers QSPI_RBDR0 to QSPI_RBDR31.
For this case it is recommended to program the QSPI_RBCT[RXBRD] bit to 1. The
QSPI_SFMSR[AHBGNT] bit is asserted immediately after any running IP Command has been finished
(QSPI_SFMSR[IP_ACC] is 0), allowing the master triggering AHB Commands to trigger AHB
Commands as soon as possible without the need to wait for the RX Buffer readout to be finished.
35.6.4 Command arbitration
In case of overlapping commands the arbitration scheme is described in the following paragraphs under
the assumption that the priority mechanism described in Section 35.6.3, Exclusive Access to Serial Flash
for AHB Commands, is not used:
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor