PXD20RM Datasheet, PDF (306/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 10-13. DSPIx_RSER Field Descriptions (continued)
Field
Description
15
Receive FIFO drain DMA or interrupt request select. Selects between generating a DMA request or
RFDF_DIRS an interrupt request. When the RFDF flag bit in the DSPIx_SR is set, and the RFDF_RE bit in the
DSPIx_RSER is set, the RFDF_DIRS bit selects between generating an interrupt request or a DMA
request.
16–31
0 Interrupt request is selected
1 DMA request is selected
Reserved.
10.8.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
The DSPIx_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred
to the TX FIFO. Refer to Section 10.9.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism,
for more information. Write accesses of 8- or 16-bits to the DSPIx_PUSHR transfers 32 bits to the
TX FIFO.
NOTE
TXDATA is used in master and slave modes.
Address: Base + 0x0034
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _CON
WT
CTAS
EOQ
CT
CNT
0
0
0
0
0
0
0 _{PCS PCS PCS}
210
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-7. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
Table 10-14 describes the fields in the DSPI push transmit FIFO register.
10-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor