PXD20RM Datasheet, PDF (376/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 11-24. INT_STATUS Field Descriptions
Field
Description
12
Interrupt signal to indicate that High threshold has been reached for plane 4(FG2plane) input
P4_FIFO_HI_FLAG buffer
13
Interrupt signal to indicate that Low threshold has been reached for plane 4(FG2plane) input
P4_FIFO_LO_FLAG buffer
14
Interrupt signal to indicate that High threshold has been reached for plane 3(FG1plane) input
P3_FIFO_HI_FLAG buffer
15
Interrupt signal to indicate that Low threshold has been reached for plane 3(FG1plane) input
P3_FIFO_LO_FLAG buffer
17
Interrupt signal which indicates that the DCU3 DMA has fetched the last pixel of data from the
DMA_TRANS_FINIS memory
H
20
IPM_ERROR
Interrupt signal which indicates that an error has occurred in the Magenta line transaction
21
PROG_END
Interrupt signal which indicates that the duration for programming of DCU3 registers and
internal memories is finished
22
Interrupt signal to indicate that High threshold has been reached for plane 2 (FGplane) input
P2_FIFO_HI_FLAG buffer
23
Interrupt signal to indicate that Low threshold has been reached for plane 2 (FGplane) input
P2_FIFO_LO_FLAG buffer
24
Interrupt signal to indicate that High threshold has been reached for plane 1 (BGplane) input
P1_FIFO_HI_FLAG buffer
25
Interrupt signal to indicate that Low threshold has been reached for plane 1 (BGplane) input
P1_FIFO_LO_FLAG buffer
26
Interrupt signal to indicate that CRC_ready has not been serviced and CRC has been
CRC_OVERFLOW calculated for the next frame
27
CRC_READY
Interrupt signal to indicate CRC calculation is done and ready to be compared with
precomputed CRC value by the software
28
VS_BLANK
Interrupt signal to indicate vertical blanking period. This is the period in which all the registers
that affect the visible state of the layers need to be latched. This is needed so that CPU writes
to the register while the display is being updated does not cause any errors.
29
LS_BF_VS
Lines Before Vsync interrupt. It is generated threshold LS_BF_VS number of lines ahead of the
vertical front porch (FP_V) if enabled. The CPU can program the registers after LS_BF_VS
interrupt.
30
UNDRUN
Under Run Exception Interrupt. Asserted when display needs data and output buffer filling is
lower than or equal to the OUT_BUF_LOW threshold. Interrupt is cleared when the data in the
output buffer is greater than threshold and CPU writes 1 to this bit.
31
VSYNC
Vertical Synchronize Interrupt. If enabled, an interrupt is generated at the beginning of a frame.
11.3.4.20 Interrupt Mask Register (INT_MASK)
Figure 11-23 represents the interrupt mask register.This register enables or masks corresponding interrupt.
11-42
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor