PXD20RM Datasheet, PDF (981/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-11. LINCR1 field descriptions (continued)
Field
BF
SFTM
LBKM
MME
SBDT
RBLM
SLEEP
INIT
Description
Bypass filter
0: No interrupt if ID does not match any filter
1: An RX interrupt is generated on ID not matching any filter
Notes:
• If no filter is activated, this bit is reserved.
• This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Self Test Mode
This bit controls the Self Test mode. For more details please refer to Section 27.8.2, Self Test mode.
0: Self Test mode disable
1: Self Test mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Loop Back Mode
This bit controls the Loop Back mode. For more details please refer to Section 27.8.1, Loop Back
mode.
0: Loop Back mode disable
1: Loop Back mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode
Master Mode Enable
0: Slave mode enable
1: Master mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Slave Mode Break Detection Threshold
0: 11-bit break
1: 10-bit break
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Receive Buffer Locked Mode
0: Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1: Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming message
is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Sleep Mode Request
This bit is set by software to request LINFlexD to enter Sleep mode.
This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and the
WUF bit in LINSR are set (see Table 27-14).
Initialization Request
The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset,
LINFlexD enters Normal mode when clearing the INIT bit (see Table 27-14).
CFD
1
1
0
Table 27-12. Checksum bits configuration
CCD
LINCFR
Checksum sent
1 Read/Write
0 Read-only
1 Read/Write
None
None
Programmed in LINCFR by bits CF[0:7]
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-25