PXD20RM Datasheet, PDF (1471/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

43.5.1 SIU memory map
Table 43-2 gives an overview on the SIUL registers implemented.
Table 43-2. SIUL memory map
Address
Base (0xC3F9_0000)
Base + 0x0004
Base + 0x0008
Base + (0x000C - 0x0013)
Base + 0x0014
Base + 0x0018
Base + (0x001C - 0x0027)
Base + 0x0028
Base + 0x002C
Base + 0x0030
Base + (0x0034 - 0x003F)
Base + 0x0040 -
Base + 0x01B1
Base + 0x01B2–
Base + 0x0272
Base + (0x0274–0x04FF)
Base + 0x0500 -
Base + 0x052B
Base + (0x052C–0x05FF)
Base + 0x0600 -
Base + 0x06B8
Base + (0x06BC–0x07FF)
Base + 0x0800 -
Base + 0x08B8
Base + (0x08BC–0x0BFF)
Base + 0x0C00 -
Base + 0x0C14
Base + (0x0C18–0x0C3F)
Base + 0x0C40 -
Base + 0x0C54
Base + (0x0C58–0x0C7F)
Name
—
MIDR1
MIDR2
—
ISR
IRER
—
IREER
IFEER
IFER
—
PCR0–PCR184¹
PCR185–PCR281
—
PSMI0_3–
PSMI50_53
—
GPDO0_3 -
GPDO184_187¹
—
GPDI0_3 -
GPDI184_187¹
—
PGPDO0 -
PGPDO5
—
PGPDI0 -
PGPDI5
—
Description
Reserved
MCU ID Register #1
MCU ID Register #2
Reserved
Interrupt Status Flag Register
Interrupt Request Enable Register
Reserved
Interrupt Rising Edge Event Enable
Interrupt Falling-Edge Event Enable
IFER Interrupt Filter Enable Register
Reserved
Pad Configuration Registers 0–184
Pad Configuration Registers 185–281 (used
for non-GPIO and special functions)
Reserved
Pad Selection for Multiplexed Inputs
Reserved
GPIO Pad Data Output Register
Reserved
GPIO Pad Data Input Register
Reserved
Parallel GPIO Pad Data Out Register
Reserved
Parallel GPIO Pad Data In Register
Reserved
Size
(bits)
Location
—
32 on page 43-7
32 on page 43-8
—
32 on page 43-8
32 on page 43-9
—
32 on page 43-9
32
on page
43-10
32
on page
43-11
—
16
on page
43-11
16
on page
43-13
—
32
on page
43-15
—
32
on page
43-19
—
32
on page
43-20
—
32
on page
43-21
—
32
on page
43-22
—
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
43-5