PXD20RM Datasheet, PDF (1596/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

CPU
Destination
Mode/
Pwr Ctl
Wakeup Enable
Flag
Overrun
Edge Detect
Glitch Filter
NMI Configuration Register (NCR)
Figure 49-12. NMI pad diagram
49.5.2.1 NMI management
The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits
for an NMI in a single byte (see Figure 49-4). The pad defined as an NMI can be configured by the user
to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A
setting of having both edge events disabled results in no interrupt being detected and should not be
configured.
The active NMI edge is controlled by the user through the configuration of the NREE and NFEE bits.
NOTE
After reset, NREE and NFEE are set to ‘0’, therefore the NMI functionality
is disabled after reset and must be enabled explicitly by software.
Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to
override or disable the NMI.
The NMI destination interrupt is controlled by the user through the configuration of the NDSS bits. See
Table 49-4 for details.
49-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor