PXD20RM Datasheet, PDF (1103/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

29.4.3.14 Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT, STOP, or STANDBY to RUN0…3, the
MC_ME requests the processor to exit from its halted or stopped state. This step is executed only after the
Processor and Memory Clock Enable process is completed.
29.4.3.15 System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16 MHz int. RC osc. takes effect only after the S_FIRC bit
of the ME_GS register is set by hardware (i.e., the fast internal RC oscillator (16 MHz) has
stabilized).
• The target clock configuration for the div. 4-16 MHz ext. xtal osc. takes effect only after the
S_FXOSC bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16
MHz) has stabilized).
• The target clock configuration for the primary PLL/2 takes effect only after the S_FMPLL0 bit of
the ME_GS register is set by hardware (i.e., the primary frequency modulated phase locked loop
has stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111.” This is
possible only in the STOP and TEST modes. In the STANDBY mode, the clock configuration is
fixed, and the system clock is automatically forced to ‘0’.
The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS
register, which is updated after every system clock switching. Until the target clock is available, the system
uses the previous clock configuration.
System clock switching starts only after
• the Peripheral Clocks Disable process has completed in order not to change the system clock
frequency before peripherals close their internal activities
An overview of system clock source selection possibilities for each mode is shown in Table 29-17. A ‘’
indicates that a given clock source is selectable for a given mode.
Table 29-17. MC_ME System Clock Selection Overview
System
Clock
Source
16 MHz
int. RC
osc.
div. 4-16
MHz ext.
xtal osc.
RESET

(default)
TEST

(default)

SAFE

(default)
Mode
DRUN RUN0…3 HALT

(default)

(default)

(default)



STOP

(default)
STANDBY

Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-45