PXD20RM Datasheet, PDF (715/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

address: eMIOS0 base address +0x0C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 CHDI CHDI CHDI CHDI CHDI CHDI CHDI CHDI
W
S23 S22 S21 S20 S19 S18 S17 S16
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{CHDI CHDI CHDI CHDI CHDI CHDIS CHDI CHDI 0}
0
0
0
0
0
0
0
W ^{S15 S14 S13 S12 S11}
10
S9
S8
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-7. eMIOS200 Enable Channel Register (UCDIS)
Table 18-10. UCDIS field descriptions
Field
Description
CHDIS[n]
Enable Channel [n] bit
The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock.
1 = Channel [n] disabled
0 = Channel [n] enabled
Note: Channels that occupy a pair of slots are referred to as by their lower slot number (LSB=0
standard), therefore the bits corresponding to their higher slot number are reserved and read 0.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-13