PXD20RM Datasheet, PDF (650/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

16.2.1.5 DMA Set Enable Request (DMASERQ)
The DMASERQ register provides a simple memory-mapped mechanism to set a given bit in the
DMAERQ{H,L} registers to enable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be set. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global set function, forcing the entire
contents of DMAERQ{H,L} to be asserted. If bit 7 is set, the command is ignored. This allows multiple
byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See Figure 16-6 and
Table 16-6 for the DMASERQ definition.
Register address: DMA_Offset + 0x0018
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
SERQ[0:3]
RESET:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. DMA Set Enable Request (DMASERQ) Register
Name
NOP
SERQ[0:3]
Table 16-6. DMA Set Enable Request (DMASERQ) field descriptions
Description
No Operation
Set Enable Request
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-15 Set the corresponding bit in DMAERQ{H,L}
64-127 Set all bits in DMAERQ{H,L}
16.2.1.6 DMA Clear Enable Request (DMACERQ)
The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERQ{H,L} registers to disable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAERQ{H,L} to be zeroed, disabling all DMA request inputs. If bit 7 is set, the
command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 16-7 and Table 16-7 for the DMACERQ definition.
Register address: DMA_Offset + 0x0019
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CERQ[0:6]
RESET:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-7. DMA Clear Enable Request (DMACERQ) Register
16-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor