PXD20RM Datasheet, PDF (464/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Registers
Interface
(control
descriptors
for each
layer)
Slave bus I/F
Layer0
Layer1
Layer2
Layer3
BGCOLOR
CLUT/
Palette
RAM
(512x32)
Cursor
RAM
(1 KB)
Gamma
RAM
(256 x 8 x3)
AHB
Master
I/F
CH2
CH1
In FIFO
In FIFO
External
Video
Source
PDI_PCLK
PDI_HSYNC
PDI_VSYNC
PDI[17:0]
Parallel
data
Interface
Pixel
Format
Converter
Blending
Gamma
Correction
out
FIFO
TFT
Display _display
Driver
CRC_ready interrupt
CRC pos
CRC value
Timing signals to other modules
Signature
Calculator
MUX _{PCLK, HSYNC, VSYNC}
dcu_clk _{Timing and}
pix_clk_in _Control
pdi_clk
Unit
Mode
Figure 12-1. DCULite block diagram
The block diagram comprises two distinct sections. The lower section shows the functional blocks of the
DCULite that fetch the graphic and video content and drive the TFT LCD panel. The upper section
describes the user interface through which the user configures the graphical content of the TFT LCD panel.
The sections are analogous to the structure of communications modules, such as the FlexCAN, where one
part of the module is configured to connect with the communications bus through bit-timing, parity, baud
rate, etc., while a different part is used to store the data content and message identifiers.
12-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor