PXD20RM Datasheet, PDF (1591/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

49.4.2.3 Wakeup/Interrupt Status Flag Register (WISR)
This register holds the wakeup/interrupt flags.
NOTE
Not all bits are available in all packages.
Address: 0x0014
Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R_{0 0 0 0 0 0}
W
w1c
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 49-5. Wakeup/Interrupt Status Flag Register (WISR)
Table 49-5. WISR Field Descriptions
Field
EIFx
Description
External Wakeup/Interrupt Status Flag x.
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
1 An event as defined by WIREER and WIFEER has occurred
0 No event has occurred on the pad
NOTE
Status bits associated with on-chip wakeup sources are located to the left of
the external wakeup/interrupt status bits and are read only. The wakeup for
these sources must be configured and cleared at the on-chip wakeup source.
Also, the configuration registers for the external interrupts/wakeups do not
have corresponding bits.
49.4.2.4 Interrupt Request Enable Register (IRER)
This register is used to enable the interrupt messaging from the wakeup/interrupt pads to the interrupt
controller.
NOTE
Not all bits are available in all packages.
Address: 0x0018
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R_{0 0 0 0 0 0}
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Figure 49-6. Interrupt Request Enable Register (IRER)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
49-7