PXD20RM Datasheet, PDF (311/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

DSPI Master
Shift register
Baud rate generator
SIN_x SOUT_x
SOUT_x SIN_x
SCK_x SCK_x
CS_x CS0_x
DSPI Slave
Shift register
Figure 10-11. SPI Serial Protocol Overview
The DSPI has three peripheral chip select (CSx) signals that are be used to select which of the slaves to
communicate with.
Transfer protocols and timing properties are shared by the three DSPI configurations; these properties are
described independently of the configuration in Section 10.9.5, Transfer Formats. The transfer rate and
delay settings are described in section Section 10.9.4, DSPI Baud Rate and Clock Delay Generation.
Refer to Section 10.9.8, Power Saving Features for information on the power-saving features of the DSPI.
10.9.1 Modes of operation
The DSPI modules have five available distinct modes:
• Master mode
• Slave mode
• Module disable mode
• External stop mode
• Debug mode
Master, slave, and module disable modes are module-specific modes. The external stop and debug modes
are device-specific modes.
The module-specific modes are determined by bits in the DSPIx_MCR. The device-specific modes are
modes that the entire device can enter in parallel with the DSPI being configured in one of its
module-specific modes.
10.9.1.1 Master Mode
In master mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPIx_MCR is set. The serial communications clock (SCK) is
controlled by the master DSPI. All three DSPI configurations are valid in master mode.
In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set
the transfer attributes. Transfer attribute control is on a frame by frame basis.
Refer to Section 10.9.3, Serial Peripheral Interface (SPI) Configuration for more details.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
10-25