PXD20RM Datasheet, PDF (1420/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

PWM Channel x
MnC0P
MnC0M
Motor n, Coil 0
Motor n, Coil 1
PWM Channel x + 1
MnC1P
MnC1M
Figure 41-17. Typical Dual Full H-Bridge Mode Configuration
16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable
duty cycles.
The following sequence should be used to update the current magnitude and direction for coil 0 and coil 1
of the motor to achieve consistent PWM output:
1. Write to duty cycle register x
2. Write to duty cycle register x + 1
At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle
registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten.
41.4.1.1.2 Full H-Bridge Mode
In full H-bridge mode (MCCCx[MCOM]=0x2), the PWM channels x and x + 1 operate independently.
The duty cycle working registers are updated whenever a timer counter overflow occurs.
41.4.1.1.3 Half H-Bridge Mode
In half H-bridge mode (MCCCx[MCOM] = 0x0 or 0x1), the PWM channels x and x + 1 operate
independently. In this mode, each PWM channel can be configured such that one pin is released and the
other pin is a PWM output. Figure 41-18 shows a typical configuration in half H-bridge mode.
The two pins associated with each channel are switchable between released mode and PWM output
dependent upon the state of the output mode bits MCCCx[MCOM]. See register description in
Section 41.3.2.4, Motor Controller Channel Control Register (MCCC0..11). In half H-bridge mode, the
state of the MCDCx[SIGN[4]] bit has no effect.
41-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor