PXD20RM Datasheet, PDF (1131/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

30.7.8 Nexus Reset Control
The JCOMP input that is used as the primary reset signal for the NPC is also used by the NPC to generate
a single-bit reset signal for other Nexus blocks. The single bit reset signal functions much like the IEEE
1149.1-2001 defined TRST signal but has a default value of disabled (JCOMP is pulled low during reset)
The IEEE 1149.1-2001 defines TRST to be pulled up (enabled) by default.
30.8 Initialization / application information
30.8.1 Relationship between TCK and system clock frequency
The JTAG clock (TCK) typically operates at a frequency well below the system clock frequency, as
specified in the PXD20 Microcontroller Data Sheet. In some cases, however, such as low power mode (if
the device supports low power modes), the system clock frequency may be lowered significantly from the
normal operating range. If the system clock frequency is reduced below the frequency of TCK, it will no
longer be possible to communicate with the Nexus Port Controller Port Configuration Register
(NPC_PCR).
Therefore, if the tool needs to update the NPC_PCR Low Power Debug Enable
(NPC[PCR[LP_DBG_EN]) or Low Power Synchronization bits (NPC[PCR[LP_SYNC], the TCK clock
frequency must be lowered.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-19