PXD20RM Datasheet, PDF(950/1628 Page) Freescale Semiconductor, Inc – PXD20 Microcontroller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PXD20RM Datasheet, PDF (950/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

◁

ISRx:

code to service the interrupt event

code to clear flag bit which drives interrupt request to INTC

blr # return to epilog

26.7.2.2 Hardware Vector Mode

This interrupt exception handler is useful with processor and system bus implementations which support

a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four

instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.

interrupt_exception_handlerx:

b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue

interrupt_exception_handler_continuedx:

code to create stack frame, save working register, and save SRR0 and SRR1

wrteei 1

# enable processor recognition of interrupts

code to save rest of context required by e500 EABI

bl

ISRx

# branch to ISR for interrupt with vector x

epilog:

code to restore most of context required by e500 EABI

# Popping the LIFO after the restoration of most of the context and the disabling of processor

# recognition of interrupts eases the calculation of the maximum stack depth at the cost of

# postponing the servicing of the next interrupt request.

mbar

# ensure store to clear flag bit has completed

lis

r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address

li

r4,0x0

# form 0 to write to INTC_EOIR

wrteei 0

# disable processor recognition of interrupts

stw

r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority

code to restore SRR0 and SRR1, restore working registers, and delete stack frame

rfi

ISRx:

code to service the interrupt event

code to clear flag bit which drives interrupt request to INTC

blr

# branch to epilog

26.7.3 ISR, RTOS, and Task Hierarchy

The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register

(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme

that it may have, but that priority scheme is independent and has a lower priority of execution than the

priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside

26-28

PXD20 Microcontroller Reference Manual, Rev. 1

PreliminaryâSubject to Change Without Notice

Freescale Semiconductor

▷