PXD20RM Datasheet, PDF (65/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Programmable fill levels of read and write buffers for initiating burst transfers
• Crop feature: Support for selectively reading out a part of decompressed image data taking
complete compressed data for the full image as input.
1.5.17 DRAM controller
The DRAM controller is a multi-port DRAM controller supporting SDR, LPDDR1, DDR-1, and DDR-2
memories. The DRAM controller listens to the incoming requests to the seven buses in parallel and then
sends commands to the DRAM from the highest priority bus at the current time
The seven incoming 64-bit buses are:
• DCU3
• DCULite
• e200z4d core - instruction bus
• e200z4d core - data bus
• VIU2
• GFX2D
• eDMA
The DRAM controller features the following:
• Supports CAS latency of 2, 3, and 4 clock cycles.
• Master buses
— 7 incoming master buses
— Supports 16-byte and 32-byte bursts
— Supports byte enables
— Supports 4-bit priority signal for each bus
• Write buffer contains five 32-byte entries
• Supports 16-wide and 32-wide SDR, DDR1, DDR2 and LPDDR1 DRAM devices
• Controller supports one chip select, 8-bank DRAM system
• Supports dynamic on-die termination in the host device and in the DRAM.
• Supports memory sizes as small as 64Mbit
1.5.18 Video Input Unit (VIU2)
The VIU2 is a crossbar master module accepting an ITU656 compatible video input stream on a parallel
interface, converting the pixel data to RGB or YUV format and transferring the video image to internal
frame buffer memory or external DRAM if available.
• Supports 8-bit/10-bit ITU656 video input
• Output formats:
— RGB888
— RGB565
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
1-17