PXD20RM Datasheet, PDF (433/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Tile size - 64x64 pixels
Display Size- 320 x 240 (QVGA)
Layer Size - 192 x 128 pixels
Figure 11-81. Tile Mode
11.4.5 Hardware cursor
In addition to the 16 layers, the DCU3 also provides a special layer intended for use as a cursor. This cursor
operates in 1 bpp mode and includes its own RAM area to store the graphic. The cursor may be placed at
any location on the panel and includes an automatic blink option. The hardware cursor is configured using
a dedicated control descriptor.
The size of the cursor is defined by register 1 in the control descriptor for the cursor
(CTRLDESCCURSOR_1). The register contains two bit fields, HEIGHT and WIDTH, which determine
the size and shape of the layer. Both fields are expressed in terms of the number of pixels in each
dimension. The HEIGHT is limited to a maximum of 256 pixels, and the total number of pixels cannot
exceed the number of bits in the cursor RAM (8192 bits).
Bits in the cursor RAM that are 0 become transparent on the panel. Bits that are 1 become fully opaque in
the color defined in register 3 in the control descriptor for the cursor (CTRLDESCCURSOR_3). The
DEFAULT_CURSOR_COLOR bit field is in RGB888 format.
There are restrictions on the arrangement of bits in the cursor RAM depending on how the HEIGHT and
WIDTH bit fields are configured.
• The rightmost bit in the cursor RAM (bit 31) represents the leftmost pixel on the display.
• When the cursor size is less than 32 bits, each row of the cursor is contained in a single 32-bit word
of cursor RAM. The other bits in each row must be filled with zeros.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-99