PXD20RM Datasheet, PDF (910/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 25-8. IBCR Field Descriptions (continued)
Field
Description
Tx/Rx
Transmit/Receive mode select. This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to the SRW bit in the status register. In
master mode this bit should be set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
1 Transmit
0 Receive
NOACK
Data Acknowledge disable. This bit specifies the value driven onto SDA during data acknowledge cycles
for both master and slave receivers. The I²C module will always acknowledge address matches, provided
it is enabled, regardless of the value of NOACK. Note that values written to this bit are only used when the
I²C Bus is a receiver, not a transmitter.
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
RSTA
Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the
current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if
the bus is owned by another master, will result in loss of arbitration.
1 Generate repeat start cycle
0 No effect
DMAEN
DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I²C module requires
data to be read or written to the data register. No Transfer Done interrupts will be generated when this bit
is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions
occur. The DMA mode is only valid when the I²C module is configured as a Master and the DMA transfer
still requires CPU intervention at the start and the end of each frame of data. See the DMA Application
Information section for more details.
1 Enable the DMA TX/RX request signals
0 Disable the DMA TX/RX request signals
D_RSV Reserved bit.
D This bit is writable but should be kept as value 0.
25.4.3.4 I²C Bus Status Register
Offset 0x0003
Access: Read-only any time¹
0
1
2
3
4
5
R TCF
IAAS
IBB
IBAL
0
SRW
W
w1c
Reset
1
0
0
0
0
0
Figure 25-8. I²C Bus Status Register (IBSR)
1 _{With the exception of IBIF and IBAL, which are software clearable.}
6
7
IBIF
RXAK
w1c
0
0
25-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor