PXD20RM Datasheet, PDF (819/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-2. Flash memory configuration register memory map (continued)
Offset from
FLASH_REGS_BASE
(0xC3F8_8000)
Register
0x0030 – 0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x0048 – 0x3FFF
Reserved
UT0—UTest register 0
UT0—UTest register 1
UT0—UTest register 2
UM0—User multiple input signature register 0
UM1—User multiple input signature register 1
UM2—User multiple input signature register 2
UM3—User multiple input signature register 3
UM4—User multiple input signature register 4
Reserved
Location
on page 21-23
on page 21-25
on page 21-26
on page 21-26
on page 21-26
on page 21-26
on page 21-26
on page 21-26
21.3.2 Register descriptions
This section lists the flash memory registers in address order and describes the registers and their bit fields.
21.3.2.1 Module Configuration Register (MCR)
The MCR register is shown in Figure 21-3 and Table 21-3.
Offset: FLASH_REGS_BASE + 0x0000
0
1
2
3
4
5
6
7
8
9
10
11
R0
0
0
0
0
SIZE
0
LAS
W
Reset 0
0
0
0
0
1
0
1
0
1
0
0
Access: User read/write
12
13
14
15
0
0
0 MAS
0
0
0
0
16
17
18
R EER RWE SBC
W w1c w1c w1c
Reset 0
0
0
19
20
21
22
23
24
25
26
27
28
29
30
31
0 PEAS DONE PEG 0
0
0
0
PGM PSUS ERS ESUS EHV
0
0
1
1
0
0
0
0
0
0
0
0
0
Figure 21-3. Module Configuration Register (MCR)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-7